The present disclosure relates to semiconductor devices including a field-effect transistor including a gate electrode having a metal electrode and a silicon electrode formed on the metal electrode, and methods for fabricating the same.
As the design rule of semiconductor devices is further reduced, the degree of integration of semiconductor integrated circuits has dramatically increased, and one hundred million or more field-effect transistors (FETs) can be formed on a single chip. In order to achieve a high performance transistor, not only the gate length of the transistor, but also the thickness of a gate insulating film need to be reduced. Conventionally, a silicon dioxide film or a silicon oxynitride film which is a film obtained by nitriding a silicon dioxide film has been used as a gate insulating film; however, a thin film region having an equivalent oxide thickness (EOT) equal to or less than 2 nm increases the gate leakage current, resulting in an increase in power consumption of an integrated circuit.
To address the problem, in order to reduce the EOT while reducing the gate leakage current, attention has been given to a gate insulating film made of a high dielectric constant material. Moreover, in order to further reduce the EOT, a metal inserted polysilicon stacked FET (MIPS FET) in which a metal electrode made of, e.g., titanium nitride or tantalum nitride is interposed between a silicon electrode conventionally used as a gate electrode and a gate insulating film has been often researched and developed (see, for example, Japanese Patent Publication No. 2003-023152). The MIPS FET includes the metal electrode formed under the silicon electrode (toward the gate insulating film), and thus, depletion of the silicon electrode can be reduced, thereby providing higher performance of the transistor.
The MIPS FET is achieved by forming the metal electrode having a relatively small thickness of about 5 nm under the silicon electrode conventionally used as a gate electrode and having a relatively large thickness of 50-100 nm. It is easy to allow the shape of a gate electrode, i.e., for example, the size and height of the gate electrode, to be substantially equivalent to that of the conventionally used silicon electrode, and thus, a MIPS FET has been researched and developed as one of promising gate electrode structures for FETs with design rules of 32 nm or less (see, for example, X. Chen et al., “A Cost Effective 32 nm High-k/Metal Gate CMOS Technology for Low Power Applications with Single-Metal/Gate-First Process,” Symposium on VLSI Tech., p. 88, 2008).